1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices. In particular, the present invention relates to a lithography technology using a mask.
2. Description of the Related Art
In a probe test with respect to a wafer provided with a plurality of semiconductor chips, electrical characteristics of the plurality of semiconductor chips are often tested together at a time. At this time, an appropriate test cannot be conducted if any of the chips has a short-circuit failure. In particular, such a short-circuit failure is likely to occur at a power line and a signal line in an unavailable chip (an imperfect chip) which is formed near the edge of the wafer and whose corner is lost. Such an unavailable chip affects the test for adjacent available chips. In addition, when a probe comes in contact with the unavailable chip, a large current may flow through the probe. As a result, the life of a probe card is shortened.
It is therefore necessary to take some measures for the unavailable chips in order to avoid troubles during a wafer probe test. For example, it is necessary with respect to the unavailable chips to make power supply interconnections non-conductive in advance. The following are known as conventional techniques for avoiding troubles in the wafer probe test.
According to a technique described in Japanese Laid Open Patent Application JP-P2000-124280A, a power supply interconnection is cut off prior to a wafer burn-in test. More in detail, an interconnection having a power shutdown section is provided between a bonding pad and a probing pad. Prior to the wafer burn-in test, measurement of consumption current is conducted to search for a semiconductor chip having the short circuit failure. The power shutdown section of a defective semiconductor chip is melted by laser beam irradiation, and thereby the above-mentioned interconnection is cut off electrically.
According to a technique described in Japanese Laid Open Patent Application JP-A-Heisei 9-51022, an insulating film is formed on a semiconductor chip that is confirmed to be defective prior to a wafer probe test. After that, the wafer probe test is conducted at a time for a plurality of semiconductor chips by pressing a probe card against the entire wafer.
In the above-mentioned conventional techniques, a predetermined process with regard to defective semiconductor chips is necessary after a wafer process and before the wafer probe test. That is to say, another process is required in addition to the wafer process and the test process. This leads to an increase in test costs and a decrease in throughput. It is thus desirable that the processing for the defective semiconductor chips is performed during the wafer process.
According to a technique described in Japanese Laid Open Patent Application JP-A-Heisei 7-142309, processing for the unavailable chips formed near the wafer edge is performed in an exposure process during the wafer process. In the exposure process, a pattern is projected from a reticle to a wafer by using an exposure equipment (stepper). Here, as to the chips on the periphery of the wafer, not only a normal exposure (first exposure) but also an additional exposure (second exposure) using another different pattern is performed, which is called a double exposure. For example, the different pattern for the second exposure is made by operating a reticle blind or shifting the position of the reticle. Alternatively, the second exposure may be performed after the above-mentioned reticle is detached from the equipment. Alternatively, another reticle may be prepared for the second exposure. As a result, patterns formed in the chips on the periphery of the wafer are broken. Consequently, the chips on the periphery of the wafer are automatically sorted out as defective pieces in the subsequent wafer probe test. According to this conventional technique, it is necessary to manage the reticle and the reticle blind, which causes a decrease in throughput in the exposure process.
Japanese Laid Open Patent Application JP-P2001-168102A discloses a technique that does not require such a reticle blind operation and the like. According to the conventional technique, a photo-mask with which a “fine interconnection section” is formed is prepared for interconnection formation. In the lithography process, an interconnection pattern is formed from interconnection metal by using the photo-mask and positive resist. In a case of a normal exposure, the above-mentioned “fine interconnection section” is formed. On the other hand, in a case of a double exposure, it is possible to cut off the above-mentioned “fine interconnection section”. Alternatively, the “fine interconnection section” is not formed by increasing an exposure amount.